In a conventional integrated circuit which includes NFETs (N-channel field effect transistors) and PFETs, shallow trench isolation regions are usually formed to electrically isolate the NFETs from one another and to electrically isolate the PFETs from one another. These same shallow trench isolation regions, in combination with well doping, also electrically isolate the NFETs and the PFETs. As the spacing requirements of integrated circuits become more exacting, formation of deep wells perfectly aligned with the very narrow shallow trench isolation becomes impractical. Therefore, there is a need for a method for forming deep trench and shallow trench isolation regions in the integrated circuit.